Image Steganography using Histogram Requantization

Authors:RAVIKIRAN A R, SATHISH SHET K

0265-0270

Design of Low Power Arithmetic and Logic Unit using Reversible Logic Gates

Authors:LAKSHMIKANTHA MN, ANURADHA MG

0271-0276

Patients Monitoring Portal using Beaglebone Black

Authors:RAJESH N SWAMY, SUGUNA G C

0277-0281

Implementation of An Image Steganography Technique using X(X-OR)-Box Mapping

Authors:PRASANNAKUMAR PATIL, SATISH SHET.K

0282-0287

Design of Digital PID Controller using Fast Adders

Authors:NAVEEN T.N, S.L. MUKTHI

0288-0292

Design a Reducable Dynamic Power L2 Cache Architecture using Way Tag Information Under Write-Through Policy

Authors:ALEKHYA YANAMPALLY, M. KRISHNA, K. GOPI

0293-0298

Design and Implementation of IPv6 Protocol on FPGA

Authors:KRUTHI N K, K NIRMALA KUMARI

0299-0303

A Novel Embedded Logic Module Based On Dual Dynamic Node Hybrid Flipflop

Authors:D. SAI DIVYA, A. ANSUYAMMA

0304-0309

Implementation of Power Optimization Technique for Mixed Launch of Capture And Shift

Authors:T.GOUTHAMI1, V.MADHAVA SWAMY, D.SUDHAKAR, DR. D.NAGESWAR RAO

0310-0315

Implementation of Power Optimization Technique for Mixed Launch of Capture And Shift

Authors:T.GOUTHAMI1, V.MADHAVA SWAMY, D.SUDHAKAR, DR. D.NAGESWAR RAO

0310-0315